Modern data processing systems may perform Boolean operations on a set of signals using dynamic logic circuits. Dynamic logic circuits are clocked. During the precharge phase of the clock, the circuit is precondition, typically precharging an internal node (dynamic node) of the circuit by coupling to a power supply rail. During an evaluate phase of the clock, the Boolean function being implemented by the logic circuit is evaluated in response to the set of input signal values appearing on the inputs during the evaluate phase. (For the purposes herein, it suffices to assume that the input signals have settled to their “steady-state” values for the current clock cycle, recognizing that the input value may change from clock cycle to clock cycle.) Such dynamic logic may have advantages in both speed and the area consumed on the chip over static logic. However, the switching of the output node with the toggling of the phase of the clock each cycle may consume power even when the logical value of the output is otherwise unchanged.
This may be appreciated by referring to FIG. 1 illustrating an exemplary three-input OR dynamic logic gate. Dynamic logic 100 includes three inputs A, B and C coupled to a corresponding gate of N channel field effect transistors (NFETs) 101-103. During an evaluate phase (logic one) of clock 104, NFET 106 is turned ON, and if any of inputs A, B or C are a logic one, dynamic node 108 is pulled low (logic zero), and OUT transitions to a logic one via inverter 110. During the precharge phase (logic zero) of Clk 104, dynamic node 108 is precharged to a logic one via P channel field effect transistor (PFET) 112. Half-latch PFET 114 maintains the charge on dynamic node 108 through the evaluate phase unless one or more of inputs A, B or C is turned ON. Consequently, dynamic node 108 undergoes two discharge-precharge cycles. OUT similarly undergoes two discharge-precharge cycles, albeit with opposite phase. Because OUT is discharged during the precharge phase of dynamic node 108, even though the Boolean value of the logical function is “true”, the dynamic logic gate dissipates power even when the input signal states are unchanged.
Dynamic logic may use a footer NFET 106 or not. In the case the footer NFET 106 is not used, the inputs A, B, and C must be timed to be valid during the evaluate phase of Clk 104. Regardless, dynamic circuits rely on the ability to precharge the dynamic node to a logic one state in advance of having valid logic inputs valid. In logic circuitry with a wide input fan-in, there are many parallel paths in the form of one or more intermediate nodes that may be coupled to the dynamic node by one or more select devices. When a select device connects the intermediate nodes to the dynamic node, leakage current may make it difficult to hold the logic state on the dynamic node after completion of evaluation. This is especially true as device size decreases.
The sharp increase of leakage currents in scaled technologies severely limits the robustness of dynamic circuits, especially for high fan in wide dynamic gates, commonly employed in the performance critical units of high-performance microprocessors. A strong keeper is necessary in the pre-charged state or after the completion of evaluation to compensate for the large leakage current and to hold the right state at the dynamic node. However, the use of a strong (large) keeper results in severe contention during the evaluation phase causing significant degradation of the performance. Recently, a “conditional keeper” technique has been proposed in the art where only a small fraction of the keeper is turned ON at the onset of the evaluation phase while a large fraction of the keeper is only turned ON after a delay time and only if the dynamic output remains at a logic one. This scheme reduces the contention during evaluation and thus improves the performance of the dynamic logic gate. Furthermore, the strong keeper improves the noise margin and robustness of the dynamic logic gate. Alternatively, a programmable keeper has been proposed where the effective width of the keeper is optimally programmed based on die leakage to compensate for variations in die-to-die leakage. While effective, both of these techniques result in increased area of the dynamic logic gate and added capacitance to the dynamic node which increase cost and degrade performance.
Therefore, there is a need for a dynamic logic gate with a conditional keeper that does not significantly increase circuit area or dynamic node capacitance.